Pablo Camarillo

Pablo Camarillo is a Principal Engineer at Cisco. He is an IP architect building fabrics that carry AI: scale-up, scale-out, and scale-across. That work sits on a decade of IP routing innovation. He architected SRv6 uSID and is the lead editor of RFC 8986, unifying overlay, underlay, and services on IPv6. He later defined IP Measurements (IPM), bringing path-level SLA probing into silicon, and is now working on Lightspeed Notification (LSN) for hardware-speed failure and congestion signaling for AI/ML workloads. At NANOG he presented this end-to-end view of AI backend, frontend, and scale-across networks. He bridges the gap between silicon capabilities and network architecture, leveraging Cisco Silicon One. He contributes to FD.io VPP and SAI/SONiC. Co-author of the SRv6 book and inventor on more than 50 issued patents, he received Cisco’s Pinnacle Award in 2016 and again in 2025. On the weekends you will find him flying airplanes and mountain biking around Madrid.